reverend wrote: ↑Tue Aug 26, 2025 2:24 pm What is the control voltage feeding the VCO varicaps (measured at point P3). If this is too low (below around 3 or 4 Volts) the varicaps may be being driven into saturation and that will cause a large leap in all sorts of nasty products.

Adjusted to a perfect 3.2V now, it only dropped the 50HMz by about 0.5dB
So that was not the problem.

But

reverend wrote: ↑Tue Aug 26, 2025 2:24 pm Also the matching into the gate of the RD15 doesn't look optimal. You could try removing the 2u2 inductor and replacing it with L4, then making L4 a short circuit. You may also need to lower C31 to 33pF or less to provide a proper match.

Done... 2u2 replaced with L4.
L4 = Short.
Before I replace C31 this is the result Thanks a lot for yours and everybody's help

.

No need to replace C31 then...!

Looking good. Very slightly better than the measurements for the review sample of the original 1W/4W NRG board !

Thats nice! Been a nice topic to follow!

Now I have realized/found another problem
Example if it's been on for a while say over 30 minutes and I set the PLL circuit exactly to 'Lock'
by tuning the VCO trimmer capacitor and getting 3.2V measured at P3 (emitter of TR1).
Then turn off completely wait 15 seconds then turn back on and the PLL locks in +/- 7 seconds.
Now...
If I then turn off for a minimum of say 30 minutes minimum then turn back on it take at least 90 seconds to get a PLL lock
and the 3.2V which was at P3 (emitter of TR1) will start at say 2.4V then slowly creep up to 3.2V when lock happens. Also the VCO PLL lock/un-lock system is very sensitive
Say if I go near or touch the heatsink of the driver TR6 2N4427 or many areas of the board it goes out of lock.
This problem is also worse the higher the output power above 3watts.

I have already put lots of additional supply rail filtering.
I'm guessing it could be some sort of RF creeping in to the VC0

.

Grounding issue on board?

The initial drift sounds like a heat-related issue, possibly with TR2/3 or with ZD4.

If I remember right, the Zener diode is a 7.5 Volt one? If that is the case, and with TR2/3 biassed as they are, the combined current consumption of TR2/3 should be in the order of 15 mA (7.5 mA each) which should not cause them to heat up.

However, the Zener diode has to handle about 40 mA (13.8V minus the 7.5V of the Zener divided by the 120 Ohms of R20 minus the 15 mA transistor current). The Zener is therefore dissipating about 300mW which (and I can't remember exactly which model of Zener is used) is getting close to the limit for most Zeners.

See if ZD4 is getting warm (same with R20 which is also dissipating over 300mW). If this is the case, try replacing R20 with 220 Ohms (instead of 120 Ohms) which should bring the current consumption and dissipation down significantly. This may not fix the problem but it's possible that as it heats up ZD4 is crapping out and not doing its job. You could try measuring the voltage across it when it's cold/hot first to see if this is an issue.

Of course it could be something completely different!

As for the 'touching stuff makes it go out of lock' issue, that does sound like RF getting back into somewhere or other, or being sucked off the board by your finger. Other necks may have solutions to that. One guess is that the pre-scaler (initial divider) isn't quite getting enough RF.

Sounds maybe like the loop gain of the PLL is too low, like something is wrong in the loop filter maybe. You haven't posted a schematic for the logic section yet, is it exactly the same as the original?

Also does the 5v measure correct?

Of course could also be RF pickup like others have said

To add to the checklist: try replacing C4. It may be leaky and sucking the very small bias current that comes from the 100k resistor from the loop filter.
Bad electrolytics leak more current when cold and discharged for a while.

reverend wrote: ↑Thu Sep 04, 2025 7:45 pm The initial drift sounds like a heat-related issue, possibly with TR2/3 or with ZD4.

If I remember right, the Zener diode is a 7.5 Volt one? If that is the case, and with TR2/3 biassed as they are, the combined current consumption of TR2/3 should be in the order of 15 mA (7.5 mA each) which should not cause them to heat up.

However, the Zener diode has to handle about 40 mA (13.8V minus the 7.5V of the Zener divided by the 120 Ohms of R20 minus the 15 mA transistor current). The Zener is therefore dissipating about 300mW which (and I can't remember exactly which model of Zener is used) is getting close to the limit for most Zeners.

See if ZD4 is getting warm (same with R20 which is also dissipating over 300mW). If this is the case, try replacing R20 with 220 Ohms (instead of 120 Ohms) which should bring the current consumption and dissipation down significantly. This may not fix the problem but it's possible that as it heats up ZD4 is crapping out and not doing its job. You could try measuring the voltage across it when it's cold/hot first to see if this is an issue.

You're entirely right, Rev. The PLL Pro IV was going to use an LM317 to derive the 7V5, which would overcome the thermal issues completely.

reverend wrote: ↑Thu Sep 04, 2025 7:45 pm The initial drift sounds like a heat-related issue, possibly with TR2/3 or with ZD4.

If I remember right, the Zener diode is a 7.5 Volt one?
See if ZD4 is getting warm same with R20

You could try measuring the voltage across it when it's cold/hot first to see if this is an issue.

TR2/3
I have tested with a few different BF199's same slow lock from cold issue.

ZD4
Not noticeably getting warm - R20 neither.
At 0 system cold = +7.5845V - - - - with 2.4V at P3 emitter of TR1
At 2 minutes / system in Lock = +7.6059V - - - - with 3.2V at P3 emitter of TR1
At 15 minutes / system warm = +7.6212V

reverend wrote: ↑Thu Sep 04, 2025 7:45 pm As for the 'touching stuff makes it go out of lock' issue...
One guess is that the pre-scaler (initial divider) isn't quite getting enough RF.

System in Lock - using a quality 200MHz probe at x10
I measure the 50MHz at 275mv P-P on pin 11 IC4 - 74ALS74 (pre-scaler input) = 2.75V P-P
*Note* putting the scope probe on either side of C57 send the system out of lock then back in lock. .

jvok wrote: ↑Thu Sep 04, 2025 8:56 pm Sounds maybe like the loop gain of the PLL is too low, like something is wrong in the loop filter maybe. You haven't posted a schematic for the logic section yet, is it exactly the same as the original?

He told me the rest of the board was the same as the original PRO IV
I have modified the schematic with component values and my own modifications

jvok wrote: ↑Thu Sep 04, 2025 8:56 pm Also does the 5v measure correct?

Cold = +5.0211V
Warm = +5.279V

Krakatoa wrote: ↑Thu Sep 04, 2025 10:07 pm To add to the checklist: try replacing C4. It may be leaky and sucking the very small bias current that comes from the 100k resistor from the loop filter.
Bad electrolytics leak more current when cold and discharged for a while.

I'll agree a leaky C4 is a possibility ... C5 could also be the culprit

They will take a while to replace it would mean removing the complete board from the case again

.

A quick way to test leakage in caps - take the cap off the board, wire it in series with a voltmeter, and connect it to a DC voltage just a little bit below the caps rating. Wait until the reading on the voltmeter settles, then divide by the voltmeters input impedance (usually 10megohm, so divide by 10 million) - thats your leakage current in amps. This will let you measure much smaller currents than most ammeters can.

Also double check C4 is the right way round. Electrolytics connected backwards will be very leaky

C6 is another candidate for leakage although ceramics are usually better than electros

Another thing you can try is to disable the PLL and measure the oscillator drift on its own. There's a few ways to do it but one is to remove TR1 then feed 3.2v into R4/R7 junction. Start it from cold then let it warm up and see how much it drifts

Brian - you're wasting your time. Have you got the circuit diagrams for the original NRG PLL Pro III? Look at those original diagrams and change the components in the oscillator and subsequent stages to those carefully calculated by Stephen Moss when he designed it. Stephen spent many months getting it just right, and almost every component value is pretty critical. Even the varicap you've got on the board is wrong! The PLL locking issue is probably partially due to the changed varicap.

There are two further obvious flaws with the changes that have been made: The PA stage that you're trying to use was just designed for the RD06HVF, not the RD15. Use of the RD15 would require a substantial number of changes both to the bias provision and to the output matching. Also, the original PLL Pro III 2N4427 stage (that was designed to drive a broadbanded 2SC1947) will provide far too much signal to drive either FET! My RD15 output exciter drives the final with an MPSH10, which should show you just how little drive is needed.

Incidentally, the ½f breakthrough will be almost entirely due to L2, though mismatched transistors in the oscillator might also contribute. That filter coil provided a highpass characteristic, and - on the original - the ½f was no more than -78 dBc.

To get it going, I'd remove the 2N4427, disonnect the drain choke to the final, and get the oscillator and the PLL dead right before doing anything else. Once you have a suitably clean signal, you can get to work on the subsequent stages.....

Albert H wrote: ↑Sun Sep 07, 2025 5:38 pm Even the varicap you've got on the board is wrong!
The PLL locking issue is probably partially due to the changed varicap.

Yes the Varicap in the Diagram and the one that was supplied in the kit is wrong.
I have already replaced it on my board for a proper KV1330

Albert H wrote: ↑Sun Sep 07, 2025 5:38 pm The ½f breakthrough will be almost entirely due to L2,
That filter coil provided a highpass characteristic, and - on the original - the ½f was no more than -78 dBc.

The L2 on my board is Identical to an original NRG.
If you look now I have no ½f breakthrough whatsoever.

Are the associated capacitors the right values too?

One fix that works is to replace L2 with a small adjustable inductor (Stephen tried the MC108 type as I remember) and this can be tweaked to get rid of the sub- harmonic.

Albert H wrote: ↑Wed Sep 10, 2025 3:26 am Are the associated capacitors the right values too?

One fix that works is to replace L2 with a small adjustable inductor (Stephen tried the MC108 type as I remember) and this can be tweaked to get rid of the sub- harmonic.

Hi Albert...
Please look at my last post...
The one with the Graphical Representation of the RF output of the board...

It clearly states...

''If you look now I have no ½f breakthrough whatsoever''

Now with reference to the slow frequency lock from cold.
Today it took a staggering 22:36
But... If I then turn off for 10 seconds and turn it back on it only takes only 4 seconds

jvok wrote: ↑Thu Sep 04, 2025 8:56 pm Sounds maybe like the loop gain of the PLL is too low, like something is wrong in the loop filter maybe.

How/what or were do I check or measure that ?

jvok wrote: ↑Thu Sep 04, 2025 8:56 pm Also does the 5v measure correct?

Sorry I posted the wrong results before... should be

Cold = +5.0211V
Warm = +5.0279

Krakatoa wrote: ↑Thu Sep 04, 2025 10:07 pm To add to the checklist: try replacing C4. It may be leaky and sucking the very small bias current that comes from the 100k resistor from the loop filter.

I'm replacing C4 today