PLL loop filter

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OgreVorbis
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PLL loop filter

Post by OgreVorbis » Sun Jan 21, 2018 10:45 pm

Right now I am trying to build an FM transmitter based on an integrated VCO/PLL chip (not a FM stereo transmitter chip for this specific application - to be clear). Anyway, the PLL loop filter part of the chip is external so you can change it for your application. I already have the VCO/PLL working in the FM band, but I want to modulate with an audio signal. The example loop filter they have has a loop bandwidth of 40kHz and PFD frequency of 1MHz. The type is a 3rd order passive filter. Based on my research, I need to make the loop bandwidth as small as possible for the low frequency audio. I used a calculator for 3rd order passive filter and when I enter the parameters for loop bandwidth around 50Hz (so I get enough bass), the component values get way too big.

Can someone tell me what type of filter I need to use for FM (active or passive, topology, loop bandwidth)?

If I can figure this out, I should have a very simple FM transmitter with a single chip, but much less spurs than the BH chips.

Krakatoa
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Re: PLL loop filter

Post by Krakatoa » Mon Jan 22, 2018 3:57 pm

How 'big' is big for a component value?
I have seen capacitors in the 100uF range in the PLL loop filter in commercial transmitters.
However, you can complicate the design as much as you want, like having dual lock speeds selecting different loop filter bandwidths, but in the end, the only thing that matters is closed-loop stability of the system.
To address this issue, there are some programs out there, usually provided by the pll chip manufacturer, helped by design guidelines in the app notes.

OgreVorbis
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Re: PLL loop filter

Post by OgreVorbis » Mon Jan 22, 2018 5:56 pm

Thanks for the reply.
How 'big' is big for a component value?
I have seen capacitors in the 100uF range in the PLL loop filter in commercial transmitters.
OK, that's good to know. The calculator suggested something in the 300uF range for one of the caps (the others were all < 20uF), so that's not quite as far off as I thought. So I will probably need to use an electrolytic or tant there instead of ceramic? I can't find SMD ceramic caps that large.

Also there is one other thing: I didn't know what phase margin meant when I did the calculation, so I left it at the default 45 deg. I notice if I alter it though, the values change pretty drastically. What does this parameter mean and what is a reasonable value to use for it?
However, you can complicate the design as much as you want, like having dual lock speeds selecting different loop filter bandwidths, but in the end, the only thing that matters is closed-loop stability of the system.
To address this issue, there are some programs out there, usually provided by the pll chip manufacturer, helped by design guidelines in the app notes.
Hehe, I'll leave that for later. I barely know what I am doing right now.
I am using the software from Analog Devices simPLL.

Krakatoa
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Re: PLL loop filter

Post by Krakatoa » Mon Jan 22, 2018 7:21 pm

Yes, 330 uF seems a bit high, but it all depends on the timing resistors that thus cap is associated with. So, for example, if your circuit is using 1k and 330uF in series as a low pass filter, using 10k and 33uF will have the same time constant.
However, I don't advise using ceramic caps for these high capacitance values. Some dielectrics behave weird like being piezoelectric or presenting a variable capacitance according to temperature and voltage changes. Better use good quality electrolytics or tantalums.

For the rest of the design process, I found this slideshare that tells pretty much everything about Pll's:

https://www.google.es/url?sa=t&source=w ... mCJXS8Scpp

nrgkits.nz
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Re: PLL loop filter

Post by nrgkits.nz » Thu Jan 25, 2018 10:38 am

What kind of pll chip are you using? I would recommend either the TSA5511 or the MC145170 - the latter is better in my opinion as you can get reliable lock detect out of it. I've got one on my bench at the moment for a new pll board I'm doing, I'm using two 470uF capacitors in the loop filter for a slow lock time along with a NE5532 opamp fed with 30v using one of Alberts schematics to generate the 30v. I've also got a couple high value current limiting resistors in the loop filter contributing to the slow lock time which are bypassed at startup for faster lock but placed back in line once it locks. The reference pulses from the lock detect pin are fed into the CCP module on a 16F886 PIC where it counts the pulses to determine when it's in lock. Without the narrow bandwidth you'll get tilt on bass freqs, a 30hz square wave won't look like a square wave anymore and you'll get over mod and slight distortion. You should also DC couple the mpx input, and depending on your mod varicaps you'll also get some droop on the higher freqs where the stereo and RDS subcarriers sit, you can solve this with an RC in series - I usually use a 30p trimmer and adjust it until I get best stereo separation while feeding it with StereoTool, that's when you'll have a linear mod input

Albert H
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Re: PLL loop filter

Post by Albert H » Fri Jan 26, 2018 10:28 pm

All that NRGKITS.NZ said is exactly right. Getting a modulator and loop filter exactly right isn't trivial! There are whole books written on this subject.

At the original NRG / Veronica, Stephen and I spent a lot of time fiddling with the loop filter and getting lock detect to work correctly. He used to describe some of his experimental technique as "trial and terror"! He persisted in using discrete logic ICs for the PLL as he didn't want to bind customers to a single source for parts - part of the attraction of the PLL PRO III (he felt) was that all the parts were available anywhere in the world, so that if you broke something, you could order a replacement from your local component shop. The basic phase comparator we used was just an Exclusive-OR gate, though I came up with a more complex (and rather better) phase comparator and loop filter, using a dual bistable IC and a quad NAND gate IC. The advantage of my circuit was that it gave really reliable lock / unlock outputs. We planned to use my circuit on the next version of the PLL PRO.....

There are PLL loop filter design tools available on line, from Texas, Philips and National. They're fairly straightforward to apply. You'll find that you'll want a loop filter frequency that's a couple of octaves below your minimum modulating frequency (unless you're going to do some very nifty complex filters). This leads to very slow lock-up, but gives the best modulation characteristics. A common trick is to use dual-speed loop filters - a fast lock-up circuit to get the loop in the right neighbourhood, then a slow loop filter for when you want to apply modulation.
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OgreVorbis
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Re: PLL loop filter

Post by OgreVorbis » Fri Jan 26, 2018 11:17 pm

I'm testing a new PLL chip from analog devices on an evaluation board. If it doesn't go well, though, my second option is the MC145170.
The problem is that I can easily change the components on the PLL board, but it has a loop filter build on to the board with a certain topology. I could always make another board for the filter with a better topology, but I want to see how good I can get it with the current one.

Here is a diagram of the filter: Is this type of filter reasonable?
filter.png
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